1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit used as a semiconductor memory device or the like having a redundancy relief function for substituting a normal memory cell for a malfunctioning memory cell.
2. Description of the Related Art
A conventionally-known semiconductor integrated circuit includes a plurality of adjacent output circuit blocks having the same circuit layouts, i.e., shapes and areas of the output circuit blocks, positions of signal terminals thereof, etc., are the same, and a plurality of adjacent input circuit blocks having the same circuit layouts. In the conventionally-known semiconductor integrated circuit, an output signal provided from each output circuit block is input to a corresponding one of the input circuit blocks.
Further, in the case of connecting the input circuit blocks and the output circuit blocks using conductor lines, when a pitch between adjacent output circuit blocks is identical to that between corresponding adjacent input circuit blocks, the input and output circuit blocks can be connected using straight conductor lines such that a distance between the input circuit blocks and their corresponding output circuit blocks is the shortest possible, and therefore there are no unnecessary areas in the circuit layout. On the contrary, when the pitch between the adjacent output circuit blocks is not identical to the pitch between the adjacent input circuit blocks, the conductor lines for connecting the input and output circuit blocks are required to be bent so as not cross one another avoiding a short circuit, thereby increasing an area of a conductor region in which the conductor lines are provided.
One example of such a semiconductor integrated circuit having input and output circuit blocks is a flash memory which is a nonvolatile semiconductor memory. In general, the flash memory includes spare flash memory cells. When there is a malfunction in a main memory cell, the spare flash memory cell is substituted for the malfunctioning main memory cell (malfunctioning memory cell) such that data read/write operations or the like can be performed on the spare flash memory cell. By providing the spare flash memory cells, it is possible to suppress the occurrence of defects, thereby improving the yield of the flash memories. The flash memory usually uses a redundant circuit so as to substitute the spare flash memory cell for the malfunctioning memory cell. The redundant circuit includes a memory circuit for storing address information of the malfunctioning memory cell when the malfunctioning memory cell is present and a redundancy relief comparison circuit for comparing the address information of the malfunctioning memory cell and address information externally input to the redundant circuit.
In a DRAM, SRAM or the like, which are volatile semiconductor memories, a plurality of fuses made of polysilicon, metal or the like are provided. In order to store the address information of the malfunctioning memory cell, the plurality of fuses are electrically disconnected, for example. On the contrary, in the flash memory which is a nonvolatile semiconductor memory, for example, memory cells, which are nonvolatile semiconductor memory elements, are used instead of using fuses so as to store address information of a malfunctioning memory cell on which redundancy relief is performed and other information specific to the flash memory. The memory circuit using the memory cells which are the nonvolatile semiconductor memory elements is referred to as a CAM (contents addressable memory) circuit.
As shown in FIG. 2, a CAM circuit usually includes two floating gate-type transistors 2 and 3, four N-type transistors 4, 5, 6 and 7, and two P-type transistors 8 and 9.
The P-type transistor 8, the N-type transistor 4 and the floating gate-type transistor 2 are serially connected together in this order. A power supply voltage VCC is applied to a source of the P-type transistor 8. The floating gate-type transistor 2 is connected to a drain of the P-type transistor 8 via the N-type transistor 4. A ground potential Vss is applied to a source of the floating gate-type transistor 2. Similarly, the P-type transistor 9, the N-type transistor 5 and the floating gate-type transistor 3 are serially connected together in this order. The power supply voltage VCC is applied to a source of the P-type transistor 9. The floating gate-type transistor 3 is connected to a drain of the P-type transistor 9 via the N-type transistor 5. The ground potential Vss is applied to a source of the floating gate-type transistor 3.
An output Vgate is provided by a bias voltage generation circuit 10 to a gate of each of the floating gate-type transistors 2 and 3. An output VB is provided by a bias voltage generation circuit 11 to a gate of each of the N-type transistors 4 and 5. A gate of the P-type transistor 8 is connected to a node N4 to which the P-type transistor 9 and the N-type transistor 5 are connected. Agate of the P-type transistor 9 is connected to anode N3 to which the P-type transistor 8 and the N-type transistor 4 are connected. A program voltage Vprg is applied by a voltage supply circuit (not shown) to a drain of each of the N-type transistors 6 and 7. Program signals PRG1 and PRG2 are applied by their respective control circuits (not shown) to gates of the N-type transistors 6 and 7, respectively. A source of the N-type transistor 6 is connected to a node N1 to which the floating gate-type transistor 2 and the N-type transistor 4 are connected. A source of the N-type transistor 7 is connected to a node N2 to which the floating gate-type transistor 3 and the N-type transistor 5 are connected.
The CAM circuit configured as described above can store only one bit of address information of the malfunctioning memory cell on which redundancy relief is performed. A plurality of CAM circuits together store the entire address information of the malfunctioning memory cell. When the CAM circuit stores one bit of the address information of the malfunctioning memory cell, an output terminal OUT1 of the CAM circuit is connected to a redundancy relief address comparison circuit (not shown). Outputs from the plurality of CAM circuits which together store the address information of the malfunctioning memory cell are compared to an externally-input address by the redundancy relief comparison circuit. When the comparison results in a mismatch, access to a memory cell corresponding to the externally-input address is performed. When the comparison results in a match, access to the spare memory cell is performed. Also, it is possible to store information specific to the memory device, such as a device code, in the CAM circuit. In this case, the output terminal OUT1 of the CAM circuit is connected to a buffer circuit or the like.
Since the CAM circuit includes two flash memory cells each being similar to the main memory cell, a circuit layout with respect to a position in which the CAM circuit is provided, a pitch between the CAM circuits, etc., is considerably restricted by a layout of the main memory cells.
FIG. 3 is a diagram for explaining that the position of the CAM circuit is restricted by the layout of the main memory cells. In FIG. 3, the flash memory includes in a main memory region 21 a plurality of floating gate-type transistors 20 which are the flash memories constituting the main memory and are provided in a matrix form. Each control gate of the plurality of floating gate-type transistors (flash memory cells) 20 provided in one direction is connected to word lines 22 or 26 (i.e., the word lines 22 are provided in odd columns and word lines 26 are provided in even columns). The word lines 22 and 26 are connected to a word line voltage control circuit 23. When the word line voltage control circuit 23 controls an operation so as to write/read/erase data in/from/from the flash memory cell 20, the externally-input address information is decoded so as to select one of the word lines 22 or 26 corresponding to the decoded address information, and then a voltage having a prescribed value is applied to the selected word lines 22 or 26.
In FIG. 3, the CAM circuit is positioned in regions 24 or 25 which are provided so as to adjacent to the main memory region 21 along a direction perpendicular to the word lines 22 and 26. Although the position of the CAM circuit is restricted by the layout of the main memory cells, by providing the CAM circuit and the main memory cell region 21 so as to be adjacent to each other, a decoder element which constitutes the word line voltage control circuit 23 is shared by the main memory and the CAM circuit, thereby suppressing an increase in area of a semiconductor chip.
FIG. 4 is a diagram for explaining that the pitches between a plurality of CAM circuits are restricted by the layout of the main memory cells. In FIG. 4, the plurality of CAM circuits are provided in the region 25 shown in FIG. 3. Although not fully shown in FIG. 4, the plurality of CAM circuits each having a same structure as that of a CAM circuit 30 are provided along the word line voltage control circuit 23.
In FIG. 4, the sources of the N-type transistors 6 and 7 are respectively connected to the drains of the floating gate-type transistors (flash memory cells) 2 and 3 included in the CAM circuit 30. The N-type transistors 6 and 7 serve as switches for applying the voltage Vprg to the drains of the floating gate-type transistors 2 and 3. The gates of the N-type transistors 6 and 7 are respectively connected to word lines 31 and 32. Therefore, the pitches between the plurality of CAM circuits 30 are restricted by pitches between the word lines 31 and 32.
For example, as shown in FIG. 4, each CAM circuit 30 includes two flash memory cells 2 and 3. When the word lines 31 and 32 are connected to a corresponding one of two adjacent even word lines 26 among the odd word lines 22 and the even word lines 26 in the main memory region 21, the word line 31 is connected to the gate of the N-type transistor 6 included in the CAM circuit 30 and the word line 32 is connected to the gate of the N-type transistor 7 included in the CAM circuit 30, length 33 of the CAM circuit 30 along the longitudinal direction thereof corresponds to a length of 4x (i.e., four times the length of x shown in FIG. 4) of a region including the two adjacent even word lines 26. In this manner, the pitch between the word lines 31 and 32 of the CAM circuit 30 is restricted by the layout of the main memory cells, and therefore the pitches between the plurality of CAM circuits 30 are restricted by the layout of the main memory cells.
FIG. 5 shows an example of a layout of a CAM region 35 including the CAM circuits and redundancy relief address comparison circuits. In FIG. 5, the CAM region 35 includes n first CAM circuits 30, m second CAM circuits 30xe2x80x2 and n redundancy relief address comparison circuits 40 (hereinafter, simply referred to as xe2x80x9ccomparison circuit 40xe2x80x9d). Each of the n first CAM circuits 30 is connected by its respective conductor line 50 to a corresponding one of the n comparison circuits 40. Each of the m second CAM circuits 30xe2x80x2 is connected by its respective conductor line 51 to a corresponding buffer circuit or the like (not shown). Each first CAM circuit 30 stores address information of a malfunctioning memory cell on which the redundancy relief is performed. Each second CAM circuit 30xe2x80x2 stores information, such as a device code or the like, which is specific to the memory device and excludes the address information of the malfunctioning memory cell. Although the first and second CAM circuits 30 and 30xe2x80x2 store different types of information and are connected to different types of elements, they are laid out in a similar manner.
As shown in FIG. 5, when pitch p1 between adjacent first CAM circuits 30 is equal to pitch p2 between adjacent comparison circuits 40, the first CAM circuits 30 can be connected to the corresponding comparison circuits 40 using the straight conductor lines 50, and therefore no unnecessary areas are provided in the circuit layout.
FIG. 6 shows another example of the layout of the CAM region 35. In FIG. 6, pitch p1 between the adjacent CAM circuits 30 is different from pitch p2 between the adjacent comparison circuits 40 and pitches p1 and p2 satisfy a relationship p2+W=2p1, where W denotes a width (not shown) of a single conductor line 50. In this case, the first CAM circuits 30 cannot be connected to corresponding comparison circuits 40 using straight conductor lines, and therefore the conductor lines 50 are required to be bent. Because of this, conductor lines 51 connected to the CAM circuits 30xe2x80x2 are also required to be bent. This is the case regardless of whether or not the number n of the CAM circuits 30 and the number m of the CAM circuits 30xe2x80x2 are the same.
However, when the conductor lines 50 and the conductor lines 51 are bent so as to connect the CAM circuits 30 to the comparison circuits 40 and connect the CAM circuits 30xe2x80x2 to the buffer circuits or the like, a length of each of the conductor lines 50 and 51 is increased, thereby increasing the load on the conductor lines 50 and 51. Further, pitches between the adjacent conductor lines 50 and/or 51 along a direction denoted by y shown in FIG. 6 is required to be equal to or more than a prescribed minimum value P due to the necessities in a production process of the semiconductor integrated circuit (i.e., design rules). Therefore, a length along a direction denoted by y shown in FIG. 6 of a conductor region 62xe2x80x2 is longer than length L along a direction denoted by y of a corresponding conductor region of FIG. 5, thereby increasing the size of the unnecessary area in the circuit layout. As a result, an area of the semiconductor chip is increased, thereby decreasing the number of semiconductor chips which can be fabricated on a single semiconductor wafer and increasing the cost of a single semiconductor chip.
In order to prevent an increase in area of the conductor region, the use of multilayer interconnections is considered. By using the multilayer interconnections so as to provide conductor lines in different conductor layers, conductor lines can be provided so as to overlap with one another in the different conductor layers, and therefore there is no need to provide pitches between the adjacent conductor lines along the y direction of FIG. 6. Accordingly, it is possible to prevent an increase in the length along the y direction of the conductor region 62xe2x80x2 so as not to increase an area of the conductor region 62xe2x80x2 as compared to the corresponding conductor region of FIG. 5, thereby increasing the number of semiconductor chips which can be fabricated on the semiconductor wafer so as to reduce the cost of producing a single semiconductor chip.
As described above, although an area of the conductor region can be reduced by using the multilayer interconnection, there are still problems as follows.
When providing the adjacent conductor lines so as to be in the different conductor layers, a conductor formation mask is required for each conductor layer in the steps of producing the semiconductor integrated circuit, thereby increasing the cost of producing the semiconductor integrated circuit. Further, by increasing the number of the conductor layers, the number of steps required for producing the semiconductor chip is also increased, thereby significantly increasing the cost of producing the semiconductor integrated circuit and also increasing the time required for completing the production of the semiconductor wafer.
Therefore, when the increase in the production cost caused by using the multilayer interconnection cannot be counterbalanced or overbalanced by reducing the production cost because of an increase in the number of semiconductor chips which can be fabricated on the single semiconductor wafer, no satisfactory effect can be achieved by using the multilayer interconnection. This is especially a considerable problem in semiconductor memories in which an area of the semiconductor chip is mostly occupied by memory cell regions.
Further, when the multilayer interconnection is locally used so as to reduce an area of the CAM region, there is a possibility that the entire area of the semiconductor chip is increased. The semiconductor integrated circuit includes circuit blocks other than the CAM circuits in an area around the CAM region. When the same conductor layer as that used for connecting the circuit blocks other than the CAM circuits is used in the CAM region, conductor lines for connecting the circuit blocks other than the CAM circuits are required to be provided so as to avoid the CAM region, or conductor lines used in another layer are required to be used in the CAM region.
When providing the conductor lines for connecting the circuit blocks other than the CAM circuits so as to avoid the CAM region, an entire area of the semiconductor chip is increased, thereby reducing the number of semiconductor chips which can be fabricated on the single semiconductor wafer. Therefore, the cost of a single semiconductor chip is increased. Alternatively, when using conductor lines for another layer in the CAM region, as described above, the conductor formation mask is required for each conductor layer, thereby increasing the number of production steps and increasing the cost of producing the semiconductor integrated circuit.
Based on the above-described reasons, in the flash memory, there is a need to reduce an area of the conductor region included in the CAM region without using multilayer interconnections.
According to one aspect of the present invention, there is provided a semiconductor integrated circuit which includes: n first output circuit blocks and m second output circuit blocks which are provided such that adjacent first and second output circuit blocks are spaced at a regular first pitch; and n input circuit blocks provided parallel to a direction along which the first and second output circuit blocks are provided, the input circuit blocks being provided such that adjacent input circuit blocks are spaced at a regular second pitch, in which the first and second output circuit blocks are provided such that at least part of ones of the first and second output circuit blocks alternate with the other ones of the first and second output circuit blocks and each of the first output circuit blocks is connected to a corresponding one of input circuit blocks by a first conductor line such that a length of the first conductor line is shortest between the first output circuit blocks and the corresponding ones of input circuit blocks, and second conductor lines are connected to the second output circuit blocks such that each second conductor line passes through a gap between the input circuit blocks.
With the above-described structure, even when the pitch between the adjacent first and second output circuit blocks are different from that between the adjacent input blocks, by alternately positioning the first and second output circuit blocks so as to be adjacent to one another, each of the first output blocks can be connected to a corresponding one of the input circuit blocks by its respective first conductor line such that the first conductor line is kept straight and has a length which is shortest between the first output circuit blocks and the corresponding ones of input circuit blocks. As a result, it is possible to shorten the length of the conductor lines so as to reduce the load provided on the conductor line as compared to the conventional technique which connects the input and output circuit blocks by bent conductor lines. Further, it is possible to prevent a length along a direction denoted by y as shown in FIG. 6 of a conductor line region from being increased in accordance with the pitches (a minimum value P) between the conductor lines which are required due to the necessities of production processes of the semiconductor integrated circuit (i.e., design rules). Furthermore, unlike the conventional technique in which the first and second circuit blocks are not alternately provided, the second conductor lines are connected to the second output circuit blocks such that each second conductor line passes through the gap between the input circuit blocks, and therefore it is not necessary to provide the pitches (a minimum value P) between the conductor wires which are required due to the necessities of production processes of the semiconductor integrated circuit, thereby preventing an increase in a length along a direction denoted by x as shown in FIG. 6 of a region in which the second conductor lines are provided. With this structure, it is possible to reduce an area of the conductor line region, and therefore it is possible to increase the number of semiconductor chips which can be fabricated on a single semiconductor wafer without using multilayer interconnections.
In one embodiment of the invention, layouts of the first and second output circuit blocks are identical.
In another embodiment of the invention, the semiconductor integrated circuit has a redundancy relief function for substituting a normal spare memory cell for a malfunctioning memory cell, each of the first output circuit blocks is a memory circuit for storing address information of the malfunctioning memory cell, each of the input circuit blocks is a comparison circuit for comparing the address information stored in the memory circuit and externally-input address information in which when the comparison results in a mismatch, access to a memory cell corresponding to the externally-input address is performed and when the comparison results in a match, access to the spare memory cell is performed.
In still another embodiment of the invention, the second pitch is twice as long as the first pitch.
Thus, the invention described herein makes possible the advantages of providing a semiconductor integrated circuit which can reduce an area of a conductor region provided for connecting a plurality of output circuits to a plurality of input circuits without using multilayer interconnections.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.